一种适用于折叠插值型ADC的新型编码器

Novel Encoding Scheme for Folding and Interpolating ADC

提出了一种新的适用于折叠插值型ADC的高速低功耗的编码器。该编码器使用异或-或算法完成码制转换,并且利用新的串并联多米诺电路来实现。另外,还提出了一种新的宽范围的误差校正和位同步方法应用于此编码器中。仿真结果表明,此种新型编码器的功耗延迟积比常用的ROM编码器降低了约56%,而且更适用于较高位数的折叠插值型ADC中。

A novel encoding scheme with high speed and low power is proposed for folding and interpolating ADC. In the eneoder, XOR-OR encoding algorithm and a novel serial-parallel Domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has about 56% decrease on power delay product compared to conventional ROM encoder and this encoder is more applicable for the folding and interpolating ADC with higher resolution.