摘要
针对当前RTL综合面对的挑战,总结了实际项目中的经验,可以使综合工具在更少的时间里产生的网表芯片面积更小、速度更快,而功耗更低。
This paper discusses some rules that have been deployed for RTL synthesis that Significantly improves throughput. In particular shows, the techniques presented in this paper get faster, smaller and cooler chips in less time.
