高阶数字滤波器分布式算法结构比较

Comparison between distributed arithmetic architectures of high-order digital filters

基于FPGA,对高阶FIR滤波器两种算法——"基于查找表(LUT)的分布式算法"和"改进的分布式算法"的功能及结构差异进行类比。"改进的分布式算法"是对"基于LUT分布式算法"在减少存储器技术上的改进。对于一个高阶滤波器来说,"改进的分布式算法"比"基于LUT的分布式算法",需要更少的存储器和系统资源。减少存储器使用的递归反复技术极大地增加了在FPGA平台上可实现的滤波器阶数的最大值。"改进的分布式算法"不仅节省了使用的电子器件数量,而且还平衡了FPGA硬件资源中逻辑单元(LE)和存储器的使用。从FPGA的执行结果可以确定,"改进的分布式算法"可以实现一个1024抽头的FIR滤波器,且比"基于LUT的分布式算法"节省更多系统资源。

Based on FPGA a comparison between two distributed arithmetic algorithms （DA） of high-order FIR filters in function and architecture （LUT-based DA and Proposed DA） has been made. Proposed DA needs less memory and system resource than LUTobased DA due to a memory reduction technique. Recursive iteration of the memory reduction technique significantly increases the maximal number of filter order implementable on an FPGA platform by not only saving electronic devices, but also balancing hardware usage between logic element （LE） and memory. FPGA imple- mentation results confirm that the proposed DA can implement a 1024-tap FIR filter with significantly smaller area usage than LUT-based DA.