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一种基于90nm工艺的10位电荷再分配型逐次逼近模数转换器IP 被引量：1

10-bit Charge Redistribution Successive Approximation Analog-to-Digital Converter IP Based on 90 nm Process
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摘要 在比较了三种不同的分段式全电容D/A结构的基础上,介绍了一种10bit电荷再分配型逐次逼近A/D转换器IP的设计。该转换器采用UMC 90nm SP-RVT CMOS工艺。该转换器IP的特点是采用了一种利用边缘效应的边缘电容器来代替代价昂贵的PIP和MIM电容器,提高了该IP的工艺兼容性,降低了成本。后仿真结果显示,此A/D转换器在1Msam-ple/S的速度下,有效位数可达9.6bit,功耗仅为500μW。 Compared with three kinds of segmented all C D/A structures, this paper presents one 10-bit charge redistribution successive approximation A/D converter IP with UMC 90 nm SP-RVT CMOS process. The advantage of the converter IP is using fringe capacitor replacing the high-cost PIP and MIM capacitors. This method improves compatibleness and reduces the cost of the converter IP. The post-simulation shows that the converter can work at speed of 1 Msamlpe/S, has ENOB of 9.6 and only consumes power of 500 μW.
作者 徐峰 陈杉 李小珍 杨银堂
机构地区 秉亮科技苏州有限公司 西安电子科技大学微电子学院宽禁带半导体材料与器件教育部重点实验室
出处 《电子器件》 CAS 2009年第3期596-600,共5页 Chinese Journal of Electron Devices
基金 国家自然科学基金资助(60476046,60676009) 国家杰出青年基金资助(60725415)
关键词 IP 电荷再分配 A/D转换器 CMOS 边缘电容器 IP charge redistribution A/D converter CMOS fringe capacitor
分类号 TN402 [电子电信—微电子学与固体电子学]
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参考文献7

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同被引文献8

  • 1Kim G, Kim M K, Chang B S, et al. A Low-Voltage, Low-Power CMOS Delay Element [J]. IEEE Journal of Solid-State Circuits, 1996,31(7) :966-971.
  • 2Lee S K, Park S J, Park H J, et al. A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low- Power Sensor Interface [ J ]. IEEE Journal of Solid- State Circuits, 2011,46(3) :651-659.
  • 3Yang R J, Liu S I. A 40-550 MHz Harmonic-Free All-Digital De- lay-Locked Loop Using a Variable SAR Algorithm [ J ]. IEEE Jour- nal of Solid-State Circuits, 2007,42 (2) : 361-373.
  • 4Verma N, Chandrakasan A. An Ultra-Low Energy 12-bit Rate- Resolution Scalable SAR ADC for Wireless Sensor Nodes [J]. IEEE J Solid-State Circuits, 2007,42(6) : 1196-1205.
  • 5Xu R, Liu B, Yuan J. Digitally Calibrated 768-kS/s 10-b Mini- mum- Size SAR ADC Array with Dithering [J]. IEEE J Solid- State Circuits,2012 47(9) :2129-2140.
  • 6Huang G Y,Chang S J,Liu C C,et al. A 1-08W 10-bit 200-kS/s SAR ADC with a Bypass Window for Biomedical Applications [J].IEEE Journal of Solid-State Circuits, 2012,47 ( 1 1 ) : 2783-2795.
  • 7陈娟,陈鑫.适用于数字锁相环的快速建模方法[J].电子器件,2012,35(5):535-539. 被引量：4
  • 8施琦锋,薛晓博,何乐年.新型数模转换器时域误差校正方法[J].浙江大学学报（工学版）,2013,47(11):2025-2030. 被引量：3

引证文献1

电子器件
2009年 第3期

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