Camellia加密算法基于硬件实现的优化

Optimization of Hardware Camellia Cipher Algorithm Implementation

分别从整体和局部的角度,提出Camellia算法几种基于硬件编程实现的优化方法。在整体角度,以轮循环和模块复用方式实现紧凑型结构,而以流水线方式实现高速型结构;在局部角度,提出以树形化和共享子表达式的方法减小P置换电路时延、在F函数中只实现4个S盒,达到提高处理速度、节省硬件资源的目的。

In this paper, we put forward several methods for global or partial optimization of hardware Camellia cipher algorithm im- plementation. Globally, the compact structure includes iterative loop and the high-speed structure includes pipelining. Partially, the speed could be advanced by using a tree-type structure and sharing sub-expression in P-function circuit which could effectively de- crease the delay of the critical paths; the circuit could be made more compact by using only 4 S-boxes for F-function.