系统级封装新型埋入式电源滤波结构的研究

A novel embedded power filter structure research in System-in-Package

在高密度小尺寸的系统级封装（SIP）中，对供电系统的完整性要求越来越高，多芯片共用一个电源网路所产生的电压抖动除了会影响到芯片的正常工作，还会通过供电网路干扰到临近电路和其他敏感电路，导致芯片误动作，以及信号完整性和其他电磁干扰问题。这种电压抖动所占频带相当宽，几百MHZ到几个GHz的中频电源噪声普通方法很难去除。结合埋入式电容和电源分割方法的特点，提出一种新型高性能埋入式电源低通滤波结构直接替代电源／地平面。研究表明，在0．65～4GHz的频带内隔离深度可达-40～75dB，电源阻抗均在0．250hm以下，实现了宽频高隔离度的高性能滤波作用。分别用电磁场和广义传输线两种仿真器模拟，高频等效电路模型分析这种低通滤波器的工作原理以及结构对隔离性能的影响，并进行了实验验证。

In system-in-package （SIP）or system-on-package（SoP）, the integrality of power distribution network（PDN）is required. However, multi-chips in the SiP/ SoP produce serious simultaneous switching noise （SSN）or ground bounce noise （GBN）which interfere the work of chips, and disturb circuitry and other sensitive devices nearby through interconnection structures. To reduce such interference is not easy by traditional approaches. Combing a planar embedded capacitor and power plane segmentation method, a novel low-pass filter in replacement of power/ ground planes and the equivalent circuit model are proposed in this paper. The study showed the isolation from -40 dB to -75 dB in frequency band of 0.65 MHz to 4 GHz, and the impedances of the PDN are below 0.25 ohm in the whole band. The novel low-pass filter was studied with both simulators of electromagnetic field and circuit theory. The results from both measurement and simulation were matched well.