全差分高速低电压锁存比较器的设计

Design of the fully differential high speed low voltage latched comparator

全差分锁存比较器在各种模数转换器中有着广泛的应用,其失调电压对于模数转换的精度有着直接的影响。本文提出了一种全差分高速低电压锁存比较器,着重对其失调电压和速度进行了优化。在0.25μm标准CMOS IHP工艺条件下,采用了Cadence Spectre进行了仿真,结果表明,当工作频率为200MHz,供电电压为1.5V,延时仅为1.81ns,失调电压为27.69mV。

The fully differential comparator with low offset is indispensable for a high-perforrmnce analog-to-digital converter. This paper describes a high speed low voltage latched comparator, which emphasizes on the optimization of the offset voltage and speed. The prototype is designed in 0. 25μm CMOS IHP process with a supply voltage of 1. 5 V and with the sampling frequency of 200 MHz. The spectre simulation results show that the propagation delay is only 1.81 ns and the offset voltage is 27. 69 mV.