期刊文献+

粗粒度数据流网络处理器体系结构及原型系统设计

Coarse-Grained Dataflow Network Processor:Architecture and Prototype Design
下载PDF
导出
摘要 网络处理器是一种支持高速报文处理和转发的可编程通信集成电路.作为路由器中的重要组件,网络处理器设计不但强调高性能,还要求足够的灵活性以支持未来的网络协议.针对控制流网络处理器固定拓扑结构及指令级并行性开发方面的不足,采用粗粒度数据流设计思想,提出了一种粗粒度数据流网络处理器体系结构及原型——DynaNP.DynaNP不但可利用处理引擎内控制流执行方式获得高可编程性,还利用处理引擎间数据流执行方式有效开发报文处理中的任务级并行性.此外,DynaNP提供了处理路径动态配置机制,可有效提高系统流量.DynaNP的原型系统基于SoPC技术设计实现.多个PE和功能模块通过片上高速通信网络连接,其中,核心处理引擎采用嵌入式RISC处理器核LEON3实现,并采用指令集扩展技术优化网络协议处理.该原型系统可有效验证粗粒度数据流网络处理器的功能和关键技术. Network processors (NPs) are programmable, highly integrated communications circuits optimized to support packet processing and forwarding at high rate. As an important component of routers, the design of network processors addresses the requirement of high performance while maintaining the flexibility to accommodate the future network protocols. Aimed at the limitation of ILP exploitation and the fixed topology of control-flow NP, a novel scheme and prototype of coarse- grained dataflow NP architecture--DynaNP is proposed. DynaNP not only improves the programmability of the entire NP by utilizing the controi-fiow structure of each processing element (PE), but also effectively exploits the task-level parallelism by introducing data-flow model into the processing among the PEs. A mechanism of dynamic configurable processing path is also provided in DynaNP to improve the overall throughput of the system. Moreover, the prototype system of DynaNP is introduced in this paper. The prototype system is designed based on SoPC (system on programmable chip). Multiple PEs and several functional modules are connected by on-chip communication network. The PEs are implemented by utilizing the embedded RISC processor core LEON3. And, the instruct-set of the LEON3 is extended to accelerate the processing of network protocols. The basic functions and the key techniques of DynaNP can be investigated through the prototype system.
出处 《计算机研究与发展》 EI CSCD 北大核心 2009年第8期1278-1284,共7页 Journal of Computer Research and Development
基金 国家"九七三"重点基础研究发展计划基金项目(2003CB314802)~~
关键词 网络处理器 体系结构 报文处理 粗粒度数据流 network processor architecture packet processing coarse-grained dataflow
  • 相关文献

参考文献1

二级参考文献11

  • 1王祚栋,魏少军.SOC时代低功耗设计的研究与进展[J].微电子学,2005,35(2):174-179. 被引量:19
  • 2岳虹,沈立,戴葵,王志英.基于TTA的嵌入式ASIP设计[J].计算机研究与发展,2006,43(4):752-758. 被引量:9
  • 3赵学秘,王志英,岳虹,陆洪毅.传输触发体系结构指导下的ASIP自动生成[J].计算机辅助设计与图形学学报,2006,18(10):1491-1496. 被引量:2
  • 4C Katsinis.A segmented-shared-bus multicomputer architecture[C].The 9th Int'l Conf on Parallel and Distributed Computing and Systems (PDCS' 97),Washington,1997
  • 5C H Yeh,B Parhami.Design of high-performance massively parallel architectures under pin limitations and non-uniform propagation delay[C].The 2nd AIZU Int'l Symp on Parallel Algorithms/Architecture Synthesis (PAS ' 97),Aizu-Wakamatsu,1997
  • 6K Keutzer,S Malik,A R Newton.From ASIC to ASIP:The next design discontinuity[C].IEEE Int'l Conf on Computer Design,Freiburg,2002
  • 7H Corporaal.Microprocessor Architectures:from VLIW to TTA[M].Chichester,West Sussex,England:John Wiley & Sons Ltd,1998
  • 8B R Rau,J A Fisher.Instruction-level parallel processing:History,overview and perspective[J].Journal of Supercomputing,1993,7(1):9-50
  • 9B Middha,V Raj,A Gangware,et al.A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units[C].The 15th Int'l Symp on System Synthesis,Kyoto,2002
  • 10D Liu,C Svensson.Power consumption estimation in CMOS VLSI chips[J].IEEE Journals of Solid-State Circuits,1994,29(6):663-670

共引文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部