摘要
为能在数字通信系统的接收端将每帧数据区分开,实现正确译码,提出一种采用FPGA实现帧同步系统的设计方案。同步保护电路的设计提高系统的可靠性,在Quartus II开发软件上用硬件描述语言实现帧同步电路设计,并给出FPGA设计的实验仿真,实验结果表明该电路系统工作正确可靠,满足设计要求。
In order to distinguish a frame data from the receiver of the digital communication system and decode correctly, the paper presents a design method of frame synchronization system on FPGA.The synchronization protection circuit improves the reliability of the system.The frame synchronization circuit is designed and implemented on Quartus II through VHDL language and the imitation and experiment of FPGA design are given.The experiment results show the circuit works accurately and reliably ,meets the system design request.
出处
《电子设计工程》
2009年第8期36-38,共3页
Electronic Design Engineering
