摘要
从系统优化以节省面积和减小功耗的目的出发,设计了一种适用于2.4 GHz Zigbee无线收发芯片的双模滤波器电路。该滤波器采用时分复用和电路复用的方法,可工作于低通滤波和复数滤波两种模式。电路采用OTA-C 7阶巴特沃思结构,利用0.18μm CMOS工艺实现。设计中,采用基于CCO锁相环的频率修调电路,以减小滤波器频率偏差。测试结果表明,低通滤波模式时,带宽为1.45 MHz,偏移3 MHz抑制为55 dB;在复数滤波模式下,镜像抑制可达35 dB;在1.8 V电源电压下,滤波器和修正电路电流分别为0.86 mA和0.23 mA。
To save area and reduce power for system optimization, a dual-mode filter was designed for a 2. 4 GHz Zigbee wireless transceiver. With time division and circuit reuse, this filter works at a low pass or a poly-phase mode. Implemented in 0. 18μm CMOS technology, the filter uses a 7th-order Butterworth OTA-C architecture. A CCO PLL-based frequency tuning circuit was adopted to minimize frequency variation. Test results showed that, in low-pass mode, the filter had a bandwidth of about 1.45 MHz, and an out-of-band rejection of 55 dB at 3 MHz offset, and in poly-phase mode, its image rejection ratio was over 35 dB. Under 1.8 V supply voltage, the filter and the tuning loop dissipates 0. 86 mA and 0. 23 mA of power, respectively.
出处
《微电子学》
CAS
CSCD
北大核心
2009年第4期478-482,共5页
Microelectronics
基金
2006年浙江省重大科技专项(2006C11107)