摘要
提出了一种简单快速的多速率位同步FPGA实现方法,该方法采用码元的上升沿或者下降沿作为触发信号对分频器进行复位来获取码元的位时钟信息。仿真及实验表明:该系统具有较快的位同步建立时间,系统工作稳定、可靠。
A simple and rapid multi - bit rate simultaneous FPOA implementation, the method used symbol of the rising edge or falling edge as a trigger signal on the Frequency divider to reset for access to the symbol-clock information. And the simulation experiments show that the system has a bit faster set-up time synchronization, system stable and reliable.
出处
《广西通信技术》
2009年第2期34-36,共3页
Guangxi Communication Technology
