0.18m CMOS中用于频率综合的时间数字转换器

Time-to-digital converter for frequency synthesis in 0.18 μm CMOS

该文提出一种应用于全数字锁相环高分辨率的时间数字转换器TDC。该TDC延时单元由两级特殊的反相器构成,其中第一个反相器只考虑上升沿,而第二个反相器只考虑下降沿,通过合理选择两级反相器的尺寸可使总延时小于传统延时单元的一半,从而提高了TDC的分辨率。针对这种只考虑单沿的延时单元,该文还提出了相应的TDC系统。实验结果表明,在0.18μm CMOS工艺下,该文提出TDC的分辨率能达到28 ps。

A time to-digital converter （TDC） was developed for high resolution frequency synthesis. The system measures only the rising edge transitions in the first inverter and the falling edge transitions in the second, so the total delay in the cell can be reduced to less than half the delay of traditional systems by choosing appropriate sizes of these transistors. The resolution can then be dramatically improved. Simulations show that the system resolution reaches 28 ps in 0.18 μm CMOS.