用于超宽带通信的低功耗4b 2GHz flash ADC

Low-power 4 b 2 GHz flash ADC for ultra-wideband communications

宽带信号的高速采集电路是超宽带(ultra-wideband,UWB)通信系统的基本单元,在满足高速采集要求的同时保持低功耗是设计的难题。该文通过改进全差分预放和高速比较器电路,设计了一个用于超宽带的4 b flash模数转换器(ADC),获得了2 GHz的采样速率,而功耗仅为38mW。基于和舰0.18μm CMOS工艺的仿真设计和流片测试结果表明,该ADC最大积分非线性(INL)和微分非线性(DNL)指标分别为+0.31/-0.28 LSB和+0.53/-0.36LSB;采样率在600 MHz以内时非杂散动态范围(SFDR)大于38 dB。所设计的ADC核心面积小于0.14 mm2。

The high-speed wide band analog to digital converter （ADC） is a key component for uhra-wideband （UWB） communication systems, but this ADC needs to have low power consumption. This paper presents a 4 b flash ADC for UWB systems, which utilizes an evolved differential preamplifier and comparator. The ADC was designed with HJTC 0.18 μm CMOS technology and achieved 2 GHz while consuming only 38 mW. The maximum INL is ＋ 0. 31/ - 0. 28 LSB, the maximum DNL is ＋ 0.53/ - 0. 36 LSB, and the spurious-free dynamic range （SFDR） is over 38 dB at 600 MHz. The ADC has a small core area of less than 0. 14 mm^2.