子阵叠加结构降低宽带阵列副瓣电平方法研究

Research of Using Overlapping Subarray Architecture For Sidelobe Reduction of Wide Band Array Antenna

对于子阵级使用延迟线,单元级使用移相器的阵列,当工作频率改变时,由于子阵级方向图中的栅瓣落入单元级方向图的主瓣区域,使阵列方向图的副瓣电平升高。通过采用子阵叠加结构可以有效降低阵列方向图的副瓣电平。仿真结果表明在子阵叠加结构中,除了在子阵级和单元级使用加权分布降低副瓣电平外,子阵叠加比决定了阵列的副瓣性能。当在子阵级和单元级使用泰勒分布,并且子阵叠加比为2时,工作在宽带、宽角下的阵列可以获得较好的副瓣性能。

For wide band array antennas using phase shifters at element level and true time delays at subarray level, sidelobe performance will deteriorate because mainlobe will be broadened in subarray pattern and grating lobe will appear in array factor. Using overlapping subarray architecture can effectively reduce array sidelobe level. Simulation results show that besides aperture distribution at element level and subarray level, the overlap ratio mainly decides the sidelobe performance. Good sidelobe performance can be achieved over wideband when subarray overlap ratio equals 2 and Taylor weight distribution is used at element and subarray stage.