基于VHDL的多功能可变模计数器设计

Design of Multi-functional Module-alterable Counter Based on VHDL

可变模计数器作为一种基本数字电路模块,在各种数字系统中应用广泛。在对现有的可变模计数器的研究基础上,在QuartusⅡ开发环境中,用VHDL语言设计一种功能更加强大的可变模计数器,它具有清零、置数、使能控制、可逆计数和可变模等功能,并且对传统的可变模计数器的计数失控问题进行研究,最终设计出一种没有计数失控缺陷的可变模计数器,并以ACEX1K系列EP1K30QC208芯片为硬件环境,验证了其各项设计功能。结果表明该设计正确,功能完整,运行稳定。

As a basic digital circuit module module- alterable counter has an abroad application in various digital systems. In the environment of Quartus Ⅱ , based on research of the existing module - alterable counter, a module - alterable counter with more functions, such as clear, set, enable control, reversible count, module- alterable count and so on, which is designed with VHDL. By researching the problem of losing control existed in traditional module- alterable counter,a module- alterable counter with no fault is designed. By using EP1K30QC208 chip of ACEX1K series,all of the functions are verified,and the result indicates that the counter is designed correctly, and has integral functions and stable operation.