超深亚微米集成电路互连线几何变异提取方法

Methodology for Ultra Deep Sub-micro Integrated Circuit Interconnect Geometric Variation Extraction

硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。这里基于电阻和电容等电学测试结构相应的数学计算公式,阐述进行互连线几何变异提取的方法,分析所采用的测试结构与计算公式的可行性,讨论误差来源,提出仿真工作与测试芯片设计原则。目的在于解决工艺建模与寄生参数建模过程中电阻和电容变异之间紧密的空间相关性,从而易于建立用于集成电路参数成品率评估计算的可制造性设计模型。

Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub- micro process nodes. Based on resistance and capacitance test structures and the corresponding equations, a methodology for interconnect geometric variation is demonstrated, the feasibility, errors and the tips for test chip designing and simulation work are analysed and discussed.