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基于高速串行通信接口的双模发送器设计

Design of Dual-Mode Serial Link Transmitter
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摘要 在通用高速串行通信接口电路设计中,高速发送器要向下兼容低速发送收器,常规方法将高速、低速发送器并行组合而成,面积大、功耗大、工作不稳定.本文基于八级主-预驱动器架构和分级"延时-开启"数据转换率控制方案,设计了一种兼容高、低速的双模发送器.电路前、后仿真基于Cadence的spectre软件,电路设计和流片基于TSMC的CMOS 0.25 um混合信号模型.基于USB2.0测试环境的仿真结果表明:发送器输出信号波形(幅值,上升、下降时间)完全遵从USB2.0的协议要求. In the design of high-speed serial link, the transmitter is generally required downward compatible with full- speed transmitter. Generally high and full-speed transmitter is designed separately, then fitted together. This method is easily used with wide area and large power consumption. It has proposed a novel dual-mode transmitter based on 8-stage drive cells and "delay-turn-on" slew rate-controlled circuits. By using TSMC 0.25 um, 2.5V CMOS mixed technology and Spectre simulator in Candence environment, the results reveal that the transmitter designed supports 12 Mbps and 480 Mbps data rate according to USB 2.0 specification. Since the transmitter contains slew rate-controlled circuits, the waveform for output signal of transmitter is inagreement with USB 2.0 specification.
出处 《河南师范大学学报(自然科学版)》 CAS CSCD 北大核心 2009年第4期55-58,共4页 Journal of Henan Normal University(Natural Science Edition)
基金 国家自然科学基金(60678045)
关键词 高速串行接口 CMOS发送器 双模 数据转换率控制 high-speed serial link CMOS transmitter dual-mode slew rate control
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参考文献4

  • 1Ricchiuti V, Orlandi A, Antonini G. High speed serial links characterization for ATCA backplanes[C]. Signal Propagation on Interconnects 2008, Washington, 2008.
  • 2Sim Jae-Yoon, Sohn Young-Soo, Park Hong-June, et al. 840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM - to- processet communication[C]. Proceedings of the 1999 Symposium on VLSI Circuits, Washington, 1999.
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  • 4Lin Chih-Hsienl, Tsai Chang-Hsiaol, Chen Chih-Ning, et al. 4/2 PAM serial link transmitter with tunable pre-emphasis[C]. 2004 IEEE International Symposium on Circuits and Systems, Piseataway,2004.

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