基于FPGA的星载计算机自检EDAC电路设计

A self-checking EDAC design based on FPGA for spacecraft computer

为了消除空间环境中单粒子翻转(SEU)的影响,目前星载计算机中均对RAM存储单元采用检错纠错(EDAC)设计。随着FPGA在航天领域的广泛应用,FPGA已成为EDAC功能实现的最佳硬件手段。本文介绍了EDAC的编码和实现,提出一种功能完善的、具有自检、自纠错功能的EDAC电路设计,并采用仿真工具对该EDAC电路的功能进行了验证。

To mitigation single-event upsets （SEU） for spacecraft computer in space environment, error detection and correction （EDAC） design is used to protect the contents of memory without exception. FPGA becomes a best hardware method of EDAC implement along with the widely use in spacecraft development. The theory and implement of EDAC is introduced in this paper, and a perfect EDAC design with self-checking and self-correcting is described. Functions of the design are simulated and verified in emulator software.