基于FPGA的半并行FIR滤波器设计

Semi-Parallel FIR Filter Design Based on FPGA

为了提高FIR滤波器的运算速度和降低的资源消耗,提出了一种新颖的半并行FIR滤波器设计方法,该方法有固定的延时,可以根据滤波器抽头数的不同,得到不同的最高数据输入速率。仿真结果表明,该滤波器设计方法在高速数字下变频器的设计中有较好的性能,并且通过优化设计,可以在一个FPGA实现多个该滤波器模块。

In order to increase FIR processing speed and reduces the resources of hardware, the paper proposes a new semi-parallel FIR filter design method, the method has fixed delay time, and can get the most input data rate based on the different filter＇s order. The simulation results show that the design method can receive a fine performance in the high rate down-converter, and could implement many the filter models in a FPGA using optimization.