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Testing content addressable memories with physical fault models

Testing content addressable memories with physical fault models
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摘要 Content addressable memory (CAM) is widely used and its tests mostly use functional fault models. However, functional fault models cannot describe some physical faults exactly. This paper introduces physical fault models for write-only CAM. Two test algorithms which can cover 100% targeted physical faults are also proposed. The algorithm for a CAM module with N-bit match output signal needs only 2N+2L+4 comparison operations and 5N writing operations, where N is the number of words and L is the word length. The algorithm for a HIT-signal-only CAM module uses 2N+2L+5 comparison operations and 8N writing operations. Compared to previous work, the proposed algorithms can test more physical faults with a few more operations. An experiment on a test chip shows the effectiveness and efficiency of the proposed physical fault models and algorithms. Content addressable memory (CAM) is widely used and its tests mostly use functional fault models. However, functional fault models cannot describe some physical faults exactly. This paper introduces physical fault models for write-only CAM. Two test algorithms which can cover 100% targeted physical faults are also proposed. The algorithm for a CAM module with N-bit match output signal needs only 2N+2L+4 comparison operations and 5N writing operations, where N is the number of words and L is the word length. The algorithm for a HIT-signal-only CAM module uses 2N+2L+5 comparison operations and 8N writing operations. Compared to previous work, the proposed algorithms can test more physical faults with a few more operations. An experiment on a test chip shows the effectiveness and efficiency of the proposed physical fault models and algorithms.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第8期109-115,共7页 半导体学报(英文版)
基金 supported by the National Natural Science Foundation of China (No.60603049) the National High Technology Research and Development Program of China (Nos.2008AA110901,2007AA01Z112,2009AA01Z125) the State Key Development Program for Basic Research of China (No.2005CB321600) the Beijing Natural Science Foundation (No.4072024)
关键词 content addressable memory test algorithm physical fault model content addressable memory test algorithm physical fault model
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  • 1van de Goor A J, Tlili I B S. March tests for word-oriented memories[A]. In: Proceedings of Design, Automation and Test in Europe, Paris, 1998. 501~508.
  • 2Hamdioui S, van de Goor A J, Eastwick D. Realistic fault models and test procedure for multi-port SRAMs[A]. In: Record of International Workshop on Memory Technology, Design, and Testing, San Jose, California, 2001. 65~72.
  • 3Kornachuk S, McNaughton L, Gibbins R, et al. A high speed embedded cache design with non-intrusive VIST[A]. In: Proceedings of IEEE International Workshop Memory, Technology, Design, and Testing, San Jose, California, 1994. 40~45.
  • 4Al-Assadi W K, Jayasumana A P, Malaiya Y K. On fault modeling and testing of content-addressable memories[A]. In: Proceedings of IEEE International Workshop on Memory Technology, Design and Testing, San Jose, California, 1994. 78~81.
  • 5Sidorowicz P R, Brzozowski J A, An approach to modeling and testing memories and its application to CAMs[A]. In: Proceedings of IEEE VLSI Test Symposium, Monterey, California, 1998. 411~416.
  • 6Zhao J, Irrinki S, Puri M. Testing SRAM-based content addressable memories[J]. IEEE Transaction on Computers, 2000, 49(10): 1054~1063.
  • 7Lin Kun-Jin, Wu Cheng-Wen. Functional testing of content-addressable memories[A]. In: Proceedings of International Workshop on Memory Technology, Design and Testing, San Jose, California, 1998. 70~75.
  • 8Chuang Cheng, Chih-Tsun Huang, et al. Brains: A BIST compiler for embedded memories[A]. In: Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Yamanashi, 2000. 25~27.?A?A?A?A
  • 9B Nadeau-Dostie, A Silburt, V K Agarwal. Serial interfacing for embedded-memory testing[J]. IEEE Design and Test of Computers, 1990, 7(2): 52~63.
  • 10Wu Y, Gupta S. Built-in self-test for multi-port RAMs[A]. In: Proceedings of the 16th Asian Test Symposium, Akita, 1997. 398~403.

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