FPGA面积限制下延时最小化工艺映射

An Algorithm for Technology Mapping Minimizing Delay under Area Constraints

工艺映射是FPGA设计中的关键技术，目前的研究目标是面积最小化，延时最小化和延时限制下面积最小化．然而，对任一给定的FPGA芯片，其面积大小是固定的．在固定的面积下求延时最小化工艺映射是FPGA设计中必须研究的新课题，本文首次给出这方面的成果．

Technology mapping is the key of FPGA designs. Minimizing area, minimizing delay and minimizing area under delay constraint are the common target of the designs. However, for any given FPGA chip, the area is certain. This paper presents an algorithm for technology mapping minimizing delay under area constraints.