基于IDDQ扫描的SOC可测性设计

Testability Design for SoC Based on IDDQ Scanning

超深亚微米工艺和基于可复用嵌入式IP模块的系统级芯片(SoC)设计方法使测试面临新的挑战,需要研究开发新的测试方法和策略;本文首先介绍了在CMOS集成电路中的IDDQ测试方法,介绍其基本原理,展示了测试的优越性,CMOS IC本质上是电流可测试,IDDQ和功能测试相结合,可大大改善故障覆盖率,提高测试的有效性;最后提出了一种基于IDDQ扫描的SOC可测性方案,是在SoC扫描测试中插入IDDQ的测试方法,这是一种基于BICS复用的测试技术,并给出了仿真结果最后得出结论。

The very deep sub micrometer technics and the system--on--chip （SoC） based on reusable embedded IP （intellectual property） faces new challenges for test, and the new test methodology and strategy for SoC are needed. This paper introduces basic theorem of IDDQ testing and its important character and advantages. It widely is used to measure fault that don＇t find it by using the functional test. In substance CMOS IC current can be tasted, IDDQ test can availably improve IC quality and reliability. One DFT solution for systems on chip, based on IDDQ measuring concept is presented in this paper, which is based on multiplexed use of Built-- in-- Current-- Sensor. The simula tion results obtained using Cadence Virtuoso show good performances of the solution.