12×10Gb/s CMOS并行光接收机前置放大器阵列设计

CMOS preamplifier array for a 12×10Gb/s parallel optical receiver design

采用SMIC 0.18μm CMOS工艺,设计了一种12路并行、每路工作速率为10Gb/s的光接收机前置放大器阵列,应用于高速芯片间的光互连。整个电路通过1.8V电压供电,采用RGC结构和有源电感并联峰化技术,单路中频跨阻增益为47.1dBΩ,-3dB带宽为8.9GHz。芯片工作时总的传输速率为120Gb/s。

A preamplifier array for 12 parallel optical receivers each operating at 10Gb/s is designed by using SMIC. 0.18μm CMOS technology. It can be used in optical transmission between high-speed chips. In this design, the RGC （Regulated Cascode） configuration and the shunt peaking technique using a conventional active inductor are employed. Under one supply voltage of 1.8V, each channel has a -3dB bandwidth of 8.9GHz and a transimpedance gain of 47. 1dBΩ. The total throughput of the chip is 120Gb/s.