基于FPGA的遗传算法实现

Implementation of a FPGA-based Genetic Algorithm

针对基于软件实现的遗传算法在求解问题的规模与复杂性不断扩大时,往往会速度慢、效率低下的缺点,提出了一种基于现场可编程门阵列的实现方法,并利用测试函数对算法的实现进行效果验证。实际效果显示,这种硬件实现方法,不仅结构简单,而且有效地减少了运算时间、提高了运行效率,为遗传算法能在一些实时、高速的场合得到应用提供了依据。

This paper presents the architecture of a FPGA-based genetic algorithm, a genetic algorithm written in Verilog HDL and intended for a hardware implementation. The hardware based genetic algorithm yields a significant speedup over which implemented by software which is especially useful when genetic algorithm is used for the scale and complexity of the problem is expanded. By analyzing the results of simulation and execution, the FPGA-based genetic algorithm reduce the operation time effectively and make it possible to be used in some high real-time and high-speed occasion.