摘要
提出一种基于Xilinx公司Virtex-5 FPGA的高速数字下变频的实现方法,使用System Generator for DSP软件实现IP Core在FPGA中的建模,通过Matlab进行了仿真验证,并下载到FPGA芯片中进行了功能验证,证明该设计集成度高和稳定性强,降低了开发成本.
A method of high-speed digital down conversion based on Xilinx Virtex-5 FPGA is introduced. Systemgenerator realized the design and simulating of FPGA. Projects based on FPGA will afford more stability and more integration for the system, and will reduce the cost and the exploitation time of the system.
出处
《南阳师范学院学报》
CAS
2009年第6期37-39,共3页
Journal of Nanyang Normal University
基金
南阳师范学院高层次人才科研启动费资助(nytc2006k106)