基于FPGA的R-64 FFT处理器的实现

Implementation of the 4 k point radix-64 FFT processor based on FPGA

快速傅里叶变换(FFT)处理器是大多数数字信号处理和数字通信系统的关键部件。文章实现了一种4 k(4 096)点改进的R-64(基-64)FFT处理器,相对于其他R-4的流水线结构,具有占用资源更少、控制更简单等特点。该FFT处理器采用浮点数制流水线结构,能够连续处理输入数据,对R-4处理单元的改进减少了62.5%的复数加法器;该FFT处理器基于FPGA的系统时钟能够达到89 MHz,数据吞吐量为4 096 point/46μs。

The fast Fourier transform（FFT） processor is the key to digital signal processing and telecommunication systems. A design of 4 096-point modified radix-64 FFT processor is presented, which requires less resources and needs simpler control than other radix-4 pipeline architecture. In addition, the processor adopts floating-point pipeline structure and can process input data continuously. An improved architecture of radix-4 reduces the number of complex adders by 62.5 %. An FPGA implementation of the FFT processor can operate at 89 MHz and achieve a throughput of 4 096 point/45.6 Vs.