新型高速低噪声可编程分频器的设计

Design of novel programmable divider with high speed and low noise

针对射频锁相环频率合成器对高速度和低噪声方面的要求,提出了一种适用于射频锁相环频率合成器的可编程分频器的设计方案.电路采用12级级联反馈的双模分频器结构,可以实现小于或等于8 191分频的任意分频比.基于JAZZBC35 BICMOS工艺,进行电路的设计和HSPICE仿真,在2.5 V电源电压下,功耗为1 mW.设计的可编程分频器具有大的分频比范围和良好的稳定性、灵活性,同时具有高速、低噪声等特点,适于高速锁相环频率合成器的应用.

A design scheme of programmable divider suitable for the radio frequency （RF） phase-locked loop （PLL） frequency synthesizer was presented to meet the requirement of high speed and low noise in RF PLL frequency synthesizer. The double modulus divider structure with 12 stages cascade and feedback was adopted to realize any dividing ratio equal to or less than 8 191. The circuit design and HSPICE simulation were carried out based on JAZZBC35 BICMOS with 2.5 V supply voltage and 1 mW power loss. The designed divider has a large-scale dividing ratio, good stability and flexibility. In addition, the divider with high speed and low noise can be applied in high speed PLL frequency synthesizer.