摘要
由于VHDL语言注重硬件行为描述,VHDL程序的测试方法与传统高级设计语言程序和汇编语言程序的测试方法不同。VHDL程序测试向量的自动生成方法和覆盖率测试是其功能测试中的难点。基于Matlab/Simulink的方法,将VHDL程序作为整个模型系统中的一个元件来考察,就其硬件环境进行建模,和Modelsim进行协同仿真。该方法简化了测试流程,无需采用复杂的testbench编写方法,提高了测试的完整性。
The test method for VHDL program is different from that for the programs written in high level programming language or assembly language. The difficulty in the functional testing lies in the automatic generation method of testing vectors and coverage testing. In this paper, the VHDL program is treated as a component in the model system and co-simulated with Modelsim software using Matlab/Simulink. This method simplifies the testing flow and improves the testing integrity, in stead of writing complex testbench.
出处
《信息与电子工程》
2009年第4期342-345,共4页
information and electronic engineering
