一种16位delta-sigma调制器的设计与实现

The Design and Achievement of a 16-bits Delta-sigma Modulator

文章介绍了一个应用于低频信号测量,3.3V单电源供电,信噪比达到96.7dB的低功耗的开关电容delta-sigma调制器的设计。根据delta-sigma结构理论以及实际应用范围,论证了采用cas-cade2-1结构3阶delta-sigma调制器的可行性,使得整个三阶结构的稳定输入范围等效于二阶调制器。文章采用自顶向下的设计方法,用simulink对3阶cascade2-1模型进行了系统级仿真,系统仿真加入了白噪声、闪烁噪声等各种低频噪声模型作为约束条件,通过精心调试仿真得到了各模块的指标。采用CSMC0.5μm双多晶三层金属工艺。主要模块包括积分器、比较器,并进行仿真验证,并与预定要求进行比较对照。文章在过采样率为256,采样频率为100kHz情况下对整个调制器电路进行了仿真,与系统仿真进行对照,能够达到16位的精度。整个调制器的静态功耗为1.7mW。

This article presents the analysis to switched-capacitor delta-sigma AD modulator with 95.7dB SNR, 3.3V single power supply, applied in low frequency signal detection, according to the theory of delta sigma architecture and the actual applied range. Demonstrate the feasibility of 3^rd modulator with cascade 2-1 architecture.This 3^rd modulator has the same steady input range as a 2^nd modulator. This paper use top-to-bottom method to design whole system. It the simulink to do behavior simulation via a 3^rd two stage cascade delta-sigma model, in system simulation, some normal noise models like white noise, flick noise and some other low frequency noise, are taken into account as constraint condition.All the requistion of the modules are taken from the system simulation. This paper design the ciucuit with CSMC 0.5 μ m double polysilicon. The major modules include switched -capacitor integrator and comparator, compare the simulation results to the system simultion requistion. The simulation is done while the sample frequency is 100kHz, over sample rate is 256. Contrast with the behavior simulation, the revolution is almolst 16-bits .The whole quiescent power drain is only 1.7mW.