摘要
文章对版图优化方法进行了研究,给出了几种版图优化的方法。通过研究发现,对于体硅而言要提高单元速度主要是通过减小源漏面积来实现;而对于SOI单元要提高速度只能通过减小单元的源漏周长来实现。通过仿真对比普通结构栅、叉指结构栅和环形结构栅的组成的反向器环振周期,可以发现采用叉指结构和环形栅结构不仅能有效减小单元面积,并且能通过减小源漏周长提高单元速度。
In this thesis, we studied the optimization of layout and offered several optimization methods. According to the research, we could decrease the S/D area to improve the speed in bulk silicon technology. But in SOI technology we must decrease the S/D perimeter to improve the speed. Comparing the simulation results, the loop gate can decrease the area and improve the speed by decreasing the S/D perimeter.
出处
《电子与封装》
2009年第8期31-33,共3页
Electronics & Packaging
