一种新的快速FPGA布局算法

New Fast FPGA Placer

在模拟退火算法的基础上,提出了一种快速FPGA布局算法.该算法先用解析模型快速确定所有宏模块及单个逻辑模块的"理想"位置,然后通过局部扩散消除模块之间的重叠,得到一个较好的初始布局方案,最后再用低温的模拟退火进一步优化,确定各模块的最终位置.实验数据表明,以目前在学术界普遍采用的平方线网总长度为目标函数,与经典的VPR算法相比,新算法大大降低了布局所耗费的时间,而不影响最终布局方案的质量.

A new fast FPGA placer which could treat both macro blocks and single blocks simultaneously is proposed. First the new placer determines the ideal position of all the blocks with analytical model, and then eliminates overlaps among blocks by local expansion. Finally, typical simulated low temperature annealing algorithm is used to optimize the placement. Experimental results show that in comparison with the popular VPR algorithm, the proposed method speeds up the placement greatly without deteriorating the quality of final placement.