一种应用于低功耗SRAM的新型预充电策略(英文)

Novel Pre-Charge Strategy for Power Efficient SRAM

针对传统预充电技术在SRAM每次读操作前都要进行预充电的方式,提出了一种新型的SRAM间歇式预充电技术,即只在位线电压较低时才充电的策略.该技术在面积不变的前提下降低了SRAM的读功耗,并且成功应用于8 KB 4路组相连cache中.为了精确验证该技术,将cache中的tag部分21×128 bit SRAM阵列及外围电路,分别采用传统预充电技术和该预充电技术进行单独仿真.Hspice的仿真结果表明,在SMIC0.18μm工艺下,工作频率为250 MHz,电源电压为1.8 V时,该技术在连续读操作过程中可以在保证读出结果正确的前提下,比传统方式节省大约24.4%的读功耗.

A low power SRAM read scheme with novel sporadic pre-charge （SP） strategy is proposed to improve the traditional SRAM pre-charge strategy which wastes energy by charging target bit lines at any read operation. The new SRAM charges only when voltages on bit lines are relatively low. This strategy reduces SRAM power while keeps its area unchanged and has been successfully applied to an 8 KB four-way set-associative cache. Two 21 × 128 bit 6-T SRAM arrays are simulated in order to strictly verify the proposed strategy. One of them adopts the proposed pre-charge structure, while the other adopts traditional pre-charge structure. Hspice simulation results show that for SMIC 0. 18 μm technology, with 1.8 V power supply and operation frequency of 250 MHz, the proposed scheme reads data correctly and save read power by approximately 24. 4 % during continuous read operations.