一种高速、低复杂度的数字校准技术

A Digital Calibration Technique with High Speed and Low Complexity

介绍了一种应用于高速高精度流水线模数转换器的数字后台校准技术.该技术基于2.5位/级的开关电容式MDAC结构,在前2级MDAC引入用于携带误差信息的随机序列,利用信号相关理论在数字域中通过累加、平均的方法提取出这些误差信息,并在最终的数字输出端补偿.该技术能够有效地减少由于电容失配和增益有限性等非理想因素的影响,提高系统的性能;同时它具有算法简单、应用灵活、不中断正常输出、工作频率高等特点.经过FPGA验证,校准后有效位数从8.5 bit提高到13.7 bit,无杂散动态范围从52.7 dB提高到108.4 dB.

A new digital background calibration technique is presented which is applied to high resolution high speed pipelined ADC. This technique is based on the structure of 2. 5-bit/stage switched-capacitor multiplying-digital-toanalog converter （MDAC）. Several random arrays adopted to carry the error information are introduced in the first two MDACs. Signal correlation theory is used to pick up the error in the digital domain through accumulation and average. Finally the error is fed back to the digital output for compensation. The arithmetic is simple and flexible, which can work at high frequency. Meanwhile it never interrupts the normal outputs. It can effectively suppress the effect caused by the capacitance mismatch and finite opap gain error, and therefore improve the conversion performance. The FPGA verification shows that after calibration ENOB increases from 8.5 bit to 13.7 bit, and the level of SFDR improves from 57.9 dB to 108.4 dB.