基于FPGA的高速时钟数据恢复电路的实现

Design of high-speed clock and data recovery circuit Based on FPGA

介绍了一种利用输出时钟在具有不同相位的时钟信号之间进行切换实现高速时钟恢复电路的方法。利用Altera公司Quartus软件提供的修改逻辑单元和逻辑块锁定及插入buffer的方法,消除了时钟切换产生的毛刺,弥补了不同相位时钟由于不同的传输延迟而造成的相位偏移。设计的电路实现了数字光端机要求的204.8MHz的工作频率。同时,分析了决定该电路工作频率的主要因素,通过仿真验证使用EP3C10E144C7芯片最高工作频率可以达到400MHz。

The paper presents a method to realize high-speed clock and data recovery circuit, which is based on the idea of utilizing output clock to make switching among the clocks whose phase are different. By using the modified logic elements, locking logic region provided by Altera＇s Quartus and inserting buffers, the burrs appearing in clock switching is eliminated and the phase offset generated from different transmitting delays of the clocks with different phases is compensated o The designed circuit achieves the operation frequency, which meet the requirement of our project. The main factor which affects the operation frequency of the presented circuits is also analyzed in this paper. The result of simulation based on the chip of EP3C 10E 144C7 shows that a highest operation frequency of 400 MHz can be achieved.