如何用OCC电路实现at-speed测试

How to Implement At-speed Test With OCC Circuit

集成电路制造技术的进步带来了越来越小的工艺尺寸,与此同时也带来了更多的和速度相关的故障。这些故障可以是由于工艺的偏差、不纯净的材料以及各种灰尘导致的。对于目前越来越多的高速芯片而言,即使一个很小的延迟故障也会影响芯片的正常工作频率,通常的由测试机提供慢速时钟的测试方法无法覆盖由于高速而带来的故障,由于这些原因,at-speed测试对于高速大规模集成电路变得至关重要。

As the manufacturing technology for ICs allow smaller and smaller geomemes,mere are more speed related defects occurring. The defects can be caused by manufacturing process anomalies, material impurities and any kind of dirt. For the fastest chips, even the smallest delay defects affect the rated frequency at which a chip can operate. For these reasons, at - speed testing has become critical for fast VLSI chips. Utilizing scan to perform the at - speed testing is a proven method to detect timing defects. In fact, at - speed scan testing has replaced at - speed functional testing for the same reasons that stuck - at scan testing replaced functional testing. And at - speed test for both logic and memory is becoming a requirement to ensure acceptable DPM rates. This paper discusses the methodology of at - speed and the clock generation circuit supporting at- speed test - OCC circuit.