基于动态元件匹配技术的改进逐次逼近ADC设计

Enhanced Successive Approximation ADC Based on Dynamic Element Matching Technique

介绍了一种低功耗、中等速度、中等精度的改进逐次逼近ADC,用于DSP的外围接口中。其中DAC采用分段电容阵列结构,节省了芯片面积,其高三位使用了动态元件匹配技术,改善了ADC的性能。比较器采用四级预放大器和Latch串联构成,并且使用了失调校准技术。数字电路采用全定制设计,辅助模拟电路完成逐次逼近过程,并且能够使ADC进入省电模式。芯片使用UMC0.18μm混合信号CMOS工艺制造,版图面积2.2mm×1.5mm。后仿真结果显示,ADC可以在1.8V电压下达到12bit精度,速度1MS/s,整个芯片的功耗为2.6mW。

A low-power, medium-speed and medium-resolution enhanced successive approximation ADC was described, which was used as an interface of DSP. Its DAC adopted a split capacitive array in order to lower chip size, which used dynamic element matching technique in the high-order 3 bits so as to improve the ADC performance. Four pre-amplifiers and a Latch consist of the comparator, and offset cancellation technique were employed. The digital logic part was full-custom designed, which coordinated the analog circuits to accomplish successive approximation and could power down the whole ADC. The chip was fabricated in UMC 0.18 μm mixed mode CMOS technology. The layout occupies an area of 2.2 mm × 1.5 mm, the post-simulation results show that the ADC achieves 12 bit at 1 MS/s sampling rate and consumes only 2.6 mW power using a 1.8 V supply voltage.