8 bit 400 MS/s CMOS折叠插值结构ADC的设计

8 bit 400 MS/s CMOS Folding and Interpolating ADC

折叠插值结构是高速ADC设计中的常用结构。提出了一种新的在折叠插值结构ADC中只对THA进行时间交织的技术,可以在基本不增加芯片功耗和面积的情况下,使ADC的系统速度提高近1倍。位同步技术可以保证粗分和细分通路之间的同步,在位同步的基础上设计了新的编码方式。基于上述技术设计了8 bit 400 MS/s CMOS折叠插值结构ADC,核心电路电流为110mA,面积仅1mm×0.8mm,Nyquist采样频率下SNDR为47.2dB,SFDR为57.1dB。

Folding and interpolating architecture are widely used in designing high-speed ADCs. A new time-interleaving technique combined with folding and interpolating techniques was presented, with which the conversion rate almost doubled while power and chip area remained. Based on bit synchronization technique, a new encoding mode was designed which could simplify coarse channel design. An 8 bit 400 MS/s CMOS folding and interpolating ADC was designed based on the techniques above. The ADC draws about 110 mA from a 1.8 V supply and the chip size is only 1 mm × 0.8 mm. The ADC achieves 47,2 dB SNDR and 57.1 dB SFDR at Nyquist input.