SET-MOS混合结构的触发器设计及应用

Design and Application of Hybrid SET-MOS Flip-flop Circuit

基于SET-MOS混合结构的或非门构建了基本RS触发器和主从式D触发器,对所设计的新型触发器电路进行了分析研究,并将其应用到寄存器和移位寄存器电路.利用SPICE对所设计的触发器电路进行仿真验证,仿真结果表明电路运行良好.该新型触发器电路与SET实现的电路相比,具有更高的驱动能力;与传统CMOS电路相比,电路的功耗仅为10-10W的数量级.

Basic RS flip-flop and master-slave D flip-flop were constructed based on the proposed basic logic circuits using hybrid SET-MOS transistors. The register and shift register were realized using master-slave D flip-flop through the analysis for designed circuits. The accuracy of the D flip-flop is validated by SPICE. The result shows that which compared with the pure SET circuit, is considerably augmented in its drive capability. Compared with the traditional CMOS circuit, the power dissipation of circuit only has magnitude 10^-10W.