基于循环映射的可重构处理器设计

Design of Reconfigurable Processor Based on the Loop Mapping

提出了一种适合循环任务执行的可重构处理器.该处理器通过循环控制器实现循环的自动执行,并采用数据分发技术和不对称先进先出缓存(FIFO)技术,将可重构阵列内部数据传输效率提高8倍.在现场可编程门阵列(FPGA)系统上验证了活动图像专家组-4的高等视频编码(H.264)中整数反离散余弦变换(IDCT)、运动估计及活动图像专家组-2(MPEG-2)中的IDCT等多种媒体核心算法.相比于类似的结构,该可重构处理器在不增加阵列规模的情况下,性能平均提升3.5倍.

A reconfigurable processor is presented to execute the loop automatically in reconfigurable cell array. Data distribution and asymmetric first in first out buffer （FIFO） can speedup the data transfer with 8 times. The hardware architecture is verified on the platform of field-programmable gate array （FPGA） with some kernel algorithms of multimedia applications such as integer invert discrete cosine transform （IDCT） and motion estimation of advanced video coding of moving pictures experts group-4 （H. 264） and IDCT of moving pictures experts group-2（MPEG-2）. With a same scale of reconfigurable array, the performance will be 3.5 times higher than the similar researches.