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Low power design of a field sequential color LCoS chip

Low power design of a field sequential color LCoS chip
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摘要 The low power design of a field sequential color (FSC) liquid crystal on silicon (LCoS) chip for near-to-eye application is presented in this paper. Dual power supplies are used in the design,that is,the supply for part of driving circuits is 3.3 V,and the one for the active matrix is 5.0 V. Serial-to-parallel conversion circuits are adopted to lower the pixel clock frequency of the chip. Also,an idle state is inserted into the pixel clock signal to decrease the switching activity factor to further reduce the power consumption. The LCoS chip is fabricated with 0.35 μm CMOS process and its power consumption is only about 300 mW. The low power design of a field sequential color (FSC) liquid crystal on silicon (LCoS) chip for near-to-eye application is presented in this paper. Dual power supplies are used in the design, that is, the supply for part of driving circuits is 3.3 V, and the one for the active matrix is 5.0 V. Serial-to-parallel conversion circuits are adopted to lower the pixel clock frequency of the chip. Also, an idle state is inserted into the pixel clock signal to decrease the switching activity factor to further reduce the power consumption. The LCoS chip is fabricated with 0.35 μm CMOS process and its power consumption is only about 300 mW.
出处 《Optoelectronics Letters》 EI 2009年第5期341-343,共3页 光电子快报(英文版)
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参考文献8

  • 1张富彬,HO Ching-Yen,彭思龙.SoC设计中的低功耗策略[J].电子器件,2007,30(2):633-637. 被引量:4
  • 2Jaejun Lee,Yunmo Chung,Chae-Gon Oh. IEEE Transac- tions on Consumer Electronics . 2001
  • 3Jaejun Lee,Yunmo Chung,Chae-Gon Oh. International Conference on Consumer Electronics . 2001
  • 4I-Yin Li,Jean-Fu Kiang. IEEE Transactions on Electron Devices . 2008
  • 5Peter C Baron. ADEAC 2006 .
  • 6Chenming Hu,Daniel Chou,Pratik Patel,Anupama Bowonder. Symposium on VLSI Technology, Systems and Applications . 2008
  • 7A.Chandrakasan,R.Brodersen.”Low Power Digital CMOS Design”[]..1995
  • 8Roy K,Prasad S.Low Power CMOS VLSI Circuit Design[]..2000

二级参考文献13

  • 1[1]Fjeldly T.A.Shur M.Threshold Voltage Modeling and the Sub-Threshold Regime of Operation of Short-Channel MOSFETs[J].IEEE Transactions on Electron Devices,Jan.1993:137-145.
  • 2[2]Sheu B J,Scharfetter D L,Ko P K.BSIM:Berkeley Short-Channel IGFET Model for MOS Transistor[J].IEEE Journal on Solid State Circuits,1987,22(4):558-566.
  • 3[3]Xu Yongjun,Luo Zuying,Chen Zhiguo.Average Leakage Current Macromodeling for Dual-threshold Voltage Circuits[C]//Proceedings of the 12th IEEE Asian Test Symposium,Xi'an,2003:196-201.
  • 4[4]Farrahi A.H,Tellez G.E,Sarrafzadeh M.Memory Segmentation to Exploit Sleep Mode Operation[C]//Proceedings of the IEEE/ACM 32nd Design Automation Conference,1995:36-41.
  • 5[5]Kobayasshi T.Sakurai T.Self-Adjusting Threshold-Voltage Scheme for Low Voltage High Speed Operation[C]//Proceedings of Custom Integrated Circuits Conference,1994:271-274.
  • 6[6]Li Fei,He Li,Saluja K K.Estimation of Maximum Power-up Current[C].Proceedings of Asia South Pacific Design Automation Conference,Bangalore,2002:51-56.
  • 7[7]Raje S.Sarrafzadeh M.Variable Voltage Scheduling[C]//Proceedings of the International Symposium on Low Power Design,1995:9-13.
  • 8[8]Stan M R,Burleson W P.Low-Power Encodings for Global Communication in CMOS VLSI[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,December 1997,5(4):444-455.
  • 9[9]Benini L,De Micheli G,Macii E,et al.Address Bus Encoding Techniques for System Level Power Optimization[C]//Proceedings of the IEEE Design Automation and Test in Europe,Paris,1998:861-866.
  • 10[10]Macii E.Dynamic Power Management of Electronic Systems[C]//Proceedings of the IEEE Design and Test of Computers,18(2),2001:6-9.

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