低成本可配置DTMB系统信道估计的VLSI实现

Low-cost and Reconfigurable VLSI Implementation of Channel Estimation for DTMB System

提出一种应用于DTMB系统信道估计的低成本可配置实现方案.在该方案中,本文所提出的基于快速Walsh变换的新型循环相关结构,在没有增加任何硬件成本的前提下,可以同时支持码长分别为256和512的两种PN序列进行相关运算.采用SMIC0.18标准CMOS工艺综合,本文所提出的信道估计循环相关器可以稳定工作在50MHz的系统时钟频率下,逻辑资源消耗为41355等效门.电路仿真结果表明本文提出的结构比已有的设计结构节省了约60%的功耗,硬件开销减少了48%.

This paper presents a power efficient reconfigurable correlator for DTMB channel estimation. In this design, a novel archi- tecture based on Fast Walsh Transform is adopted to perform cyclic correlation. By sharing memory and reusing calculation unit, the proposed reconfigurable architecture supports correlation of PN sequence with code length of 256 and 512 without any increment in hardware cost. Based on SMIC 0. 18μm standard CMOS technology, the circuit area of presented design is about 41355 gates. The simulation results show that the proposed correlator saves 60% power consumption and reduces 48% design complexity compared with those of the existed architectures.