基于Avalon总线的8051 MCU IP核的设计

Design of 8051 MCU IP core based on Avalon bus

设计了一款基于Avalon总线的8051MCU IP核。它支持MCS一51指令集,优化内部结构,通过采用流水线技术、指令映射技术、指令预取技术、微代码技术等极大地提高了IP核的工作速度,使IP核在100 MHz时钟下,能够单周期执行一条指令。本设计使用Modelsim软件完成了功能仿真和时序仿真,并在以Altera公司的Cyclone Ⅱ FPGA芯片为核心的DE2开发板上完成了硬件验证。

This paper introduces a design of Avalon-bus-based 8051 MCU IP core, which is comparable with the MCS-51 instruction set. To improve its performance, the IP core is optimized by many technologies, such as pipelining, instruction mapping, instruction pre-fetch, micro-programmable technology and so on. As a result, the speed of this IP core is greatly increased, so that it can handle one instruction in a signal cycle. The function simulation and timing simulation of this design are complished by Modelsim, while the whole design is verified on the Ahera DE2 development board.