基于FPGA的三线制同步串行通信控制器设计

Design of three-wire synchronous serial communication based on FPGA

为了简化应用系统中的三线制同步串行通信扩展接口,减小系统体积,降低系统功耗,通过研究三线制同步串行通信的原理,利用FPGA,结合硬件描述语言VHDL,设计了三线制同步串行通信控制器功能框架结构,介绍了各组成模块的功能及工作过程,并对该控制器IP核的接口信号进行了详细描述与定义,最后在Xilinx ISE和ModelSim SE平台下对该控制器IP核进行了综合和功能仿真。

In order to simplify extensible interface of three-wire synchronous serial communication in application system,minisb its volume and reduce its power,studying the mechanism of three-wire synchronous serial communication and using FPGA with VHDL,the author has designed functional frame of three-wire synchronous serial communication controller. The author has not only introduced the functions of every module and their working processes, and made description and definition of its IP core interface signals in detail,but also synthesized and simulated IP core at the platform of Xilinx ISE and ModelSim SE.