摘要
A 5-Gb/s 2 ： 1 MUX （multiplexer） with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment （APA）, has been designed and fabricated in SMIC＇s 0.18 μm CMOS technology. The chip area is 670 × 780 μm^2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.
A 5-Gb/s 2 ： 1 MUX （multiplexer） with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment （APA）, has been designed and fabricated in SMIC＇s 0.18 μm CMOS technology. The chip area is 670 × 780 μm^2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.
基金
Project supported by the National High Technology Research and Development Program of China (Nos.2007AA01Z2a5,2006AA01Z239)
