摘要
The planar patch-clamp technique has been applied to high throughput screening in drug discovery. The key feature of this technique is the fabrication of a planar patch-clamp substrate using appropriate materials. In this study, a planar patch-clamp substrate was designed and fabricated using a silicon-on-insulator （SOI） wafer. The access resistance and capacitance of SOl-based planar patch-clamp substrates are smaller than those of bulk silicon-based planar substrates, which will reduce the distributed RC noise.
The planar patch-clamp technique has been applied to high throughput screening in drug discovery. The key feature of this technique is the fabrication of a planar patch-clamp substrate using appropriate materials. In this study, a planar patch-clamp substrate was designed and fabricated using a silicon-on-insulator （SOI） wafer. The access resistance and capacitance of SOl-based planar patch-clamp substrates are smaller than those of bulk silicon-based planar substrates, which will reduce the distributed RC noise.
