摘要
Viterbi算法是用于卷积码译码的一种最大似然译码算法,广泛应用于各种数据传输系统。文章提出了一种基于FPGA的并行Viterbi译码实现方法,能在有限的资源条件下获得较高的译码速度,适于在实时要求较高的场合应用。
Viterbi algorithm is a maximum likehood algorithm for convolutional codes, which is applied to data-transimission system abroad. Paper advanced a parellel method of Viterbi decoding based on FPGA, that achieves high speed with limited resource, being fit for real time situation.
出处
《舰船电子工程》
2009年第9期32-33,71,共3页
Ship Electronic Engineering
