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RTR(Roll to Roll)方式制作25μm/25μm COF精细线路的参数优化 被引量:3

Optimize RTR(Roll to Roll)Producing Parameters for 25μm/25μm COF Fine Lines
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摘要 随着电子产品小型化和液晶显示器IC封装技术的快速发展,COF(Chip on Film)技术的应用市场得到了迅速扩大。按照片式减成方法制作的线宽/线距在50μm/50μm以下的精细线路,常常会出现导线过细或断线等缺陷。论文采用目前先进的RTR(Roll to Roll)生产工艺,选用12μm铜箔、15μm干膜,使用玻璃菲林进行图形转移,并运用正交设计法对影响精细线路品质的曝光能量、显影速度、蚀刻速度、蚀刻压力等因素进行优化试验。以精细线路的线宽和蚀刻系数作为评价标准,找出最佳参数,并分析了蚀刻压力对精细线路的影响机理。将最优化参数应用到生产中,使25μm/25μm的COF精细线路的成品率提高20%。最终实现25μm/25μm的COF精细线路的小批量生产。 With the miniaturization of electronic products and fast development of Liquid Crystal Display IC encapsulation technology, the application market of COF(Chip on Film) technology expand rapidly. When producing thinner than 50μm/50μm fine lines according to traditional method, there always are objections of gaps on line or under size lines. In this paper we adopt advanced production process of RTR(Roll to Roll), select 12μm copper foil and 15μm dry film, transfer diagram by glass film and use uniform design to optimize the factors of the exposure energy, exposure speed, etching speed and etching pressure which effect the quality of fine fines. We use the width of the fine lines and etching coefficient as estimation standards to find the perfect parameters as well as analyze the theory of etching pressure influence in producing fine lines. By applying the perfect parameters in production, the rate of finished products of the 25μm/25μm fine lines board increase 20%. Eventually, we achieve small volume production of 25μm/25μm fine lines.
出处 《印制电路信息》 2009年第9期41-45,共5页 Printed Circuit Information
基金 粤港关键领域重点突破项目(2007A090604005)
关键词 RTR 精细线路 COF 正交设计法 RTR(Roll to Roll) fine lines COF(Chio on Film) uniform design
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参考文献3

  • 1山本拓也,井上尚光.COFをとの高密度フレキシブル配缘板用電解铜箔[DFF][J].電子材料,2006,no10,p25-28.
  • 2赤堀廉一.最先端電子機器を支ぇるプリント配線板技術(材料·基材編),COF用途向けボリィミドフィルム[J].電子材料,2006,no10,p62-64.
  • 3苅宿友紀.LCDモヅコ一ル用COF基板[M].電子材料,2006,no.suppl.5,p73-78.

同被引文献29

  • 1梁志立.中国FPC的现状与未来[J].印制电路信息,2005(4):11-14. 被引量:11
  • 2Joseph Fjelstad, Flexible Circuit Technology[M]. BR Publishing, Inc, 2006.
  • 3Fuhan liu,Venky Sundaram.Ultra-Fine photoresisit image formation for next generation high-density PWB substrate.International microelectronics and packaging society.2000,NO3, p339-345.
  • 4林金堵;梁志立;陈培良.现在印制电路先进技术[M]上海:中国印制电路行业协会,201247-55.
  • 5小林;蔡积庆;龚永林.积层印制电路板[M]上海:中国印制电路行业协会,200335-41.
  • 6JALONEN P,TUOMINEN A. The applicability of electrodeposited photo resists in producing ultra-fine lines using sputtered seeding layers[J].{H}CIRCUIT WORLD,2002,(2):11-13.
  • 7田玲;李志东.蚀刻喷淋压力对精细线路制作的影响[A]深圳,2008.
  • 8SHIMIZU K,KOMATSU K,TANAKA Y. Controlled surface etching process for fine line/space circuits[A].USA:IEEE,2002.
  • 9WATANABE R,KIM H W. New circuit formation technology for high density PWB[A].USA:Curran Associates Inc,2005.
  • 10WATANABE R. Samsung's big idea[J].Circuitree,2005,(7):12-16.

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