基于DSP和CPLD电能质量监测装置的设计

Design of a power quality monitoring device based on DSP and CPLD

设计了一种基于DSP+CPLD构架的电能质量监测装置,该装置利用CPLD产生DSP外围器件的控制时序,文中详细介绍了CPLD对DSP外围器件的逻辑接口设计,通过MAX+PLUSⅡ对CPLD的控制时序进行仿真,仿真结果验证了本设计的可行性,试验测试结果表明该装置实现了多项电能质量指标的实时在线监测。

A new design of DSP＋CPLD power quality monitoring device is proposed in this paper. And the CPLD（ Complex Programmable Logic Device） is used to generate control timing between DSP and peripheral devices. In the paper, the use of CPLD in design of logic interface between DSP and peripheral devices is described in detail. The simulating result of CPLD control timing verifies the feasibility of the design and the testing results show that the device realizes on-line monitoring of power quality index.