基于VerilogHDL的数字加法器的设计比较与优化

Comparisons and Optimizations of Designs of Digital Adders Based on VerilogHDL

以加法器模块的不同实现方式为例,从模块易维护性、抗干扰性、运算速度和通用性等方面进行分析和比较,提出在用VerilogHDL硬件描述语言设计数字加法器模块时的指导原则。

Analysis and comparisons is made on the maintainability, anti-jammingability, operation speed and generality based on the different implementations of digital adders. Some general principles are proposed according to the analysis and comparisons on digital designs with VerilogHDL.