期刊文献+

岛式FPGA线长驱动快速布局算法 被引量:5

Wirelength-Driven Fast Placement Algorithm for Island Style FPGAs
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摘要 传统的FPGA布局算法需要花费大量时间,影响了FPGA物理设计效率.为了在保证布局质量的前提下缩短布局时间,提出一种岛式FPGA快速布局算法.首先考虑终端传输的迭代二划分,然后进行最小费用流初始布局和低温模拟退火的布局优化.在每一个划分层次中,考虑了线网的终端对线网权重的影响;对于每一个划分的区域,使用最小费用流来确定初始的布局;在布局的最后阶段使用低温模拟退火来提高初始布局的质量.实验结果表明,该算法布局结果的质量高、速度快. Traditional FPGA placement algorithms take much time, which decreases the FPGA physical design efficiency. In order to speed up the placement time and still keep the quality, a fast placement method for island style FPGAs is proposed, which includes recursive hi-partition with terminal propagation consideration, minimum-cost flow initial placement and low temperature simulated annealing optimization. It applies iterative binary partitioning in each level considering the terminal propagation. For each partitioned region, minimum-cost flow algorithm is used to determine the initial placement. And then the simulated annealing algorithm with low temperature is used to improve the initial placement result. Experimental results show the efficiency and effectiveness of our algorithm.
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2009年第9期1275-1282,共8页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金国际合作项目(60720106003) 国家自然科学基金重点项目(90607001)
关键词 布局 划分 最小费用流 低温模拟退火 placement partition min-cost flow simulated annealing
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参考文献12

  • 1Caldwell A E, Kahng A B, Markov I L. Can recursive bisection alone produce routable placements? [C]//Proceedings of the 37th Conference on Design Automation, Los Angeles, 2000:477-482.
  • 2Chang C C, Cong J, Xie M. Optimality and scalability study of existing placement algorithms[C] //Proceedings of the Conference on Asia South Pacific Design Automation, Kitakyushu, 2003: 325-330.
  • 3Kleinhans J M, Sigl G, Johannes F M, et al. GORDIAN: VLSI placement by quadratic programming and slicing optimization [J]. IEEE Transactions on Computer-Aided Design, 1991, 10(3): 356-365.
  • 4Sigl G, Doll K, Johannes F M. Analytical placement: a linear or a quadratic objective function? [C]//Proceedings of the 28th ACM/IEEE Design Automation Conference, San Francisco, 1991:427-432.
  • 5Betz V, Rose J. VPR: a new packing, placement and routing tool for FPGA research[C] //Proceedings of the 7th International Workshop on Field Programmable Logic and Applications, London, 1997, 1304: 213-922.
  • 6Wei Y C, Cheng C K. Ratio cut partitioning for hierarchical designs [J]. IEEE Transactions on Computer Aided Design, 1991, 10(7): 911-921.
  • 7赵长虹,陈建,周电,周晓方,孙劼.基于权重的超大规模集成电路布图规划算法[J].计算机辅助设计与图形学学报,2006,18(7):994-998. 被引量:6
  • 8Banerjee P, Sur Kolay S. Faster placer for island-style FPGAs [C] //Proceedings of the International Conference on Computing: Theory and Applications, Kolkata, 2007: 117- 121.
  • 9Banerjee P, Bhattacharjee S, Sur Kolay S, etal. Fast FPGA placement using space filling curve [C] //Proceedings of International Conference on Field Programmable Logic and Applications, Tampere, 2005:415-420.
  • 10Karypis G, Aggarwal R, Kumar V, et al. Multilevel hypergraph partitioning: applications in VLSI domain [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1999, 7(1):69-70.

二级参考文献10

  • 1杨中,董社勤,洪先龙,吴有亮.互连驱动的基于最小自由度优先原则的布局算法[J].计算机工程与设计,2004,25(6):849-852. 被引量:4
  • 2Wong D F,Liu C L.A new algorithm for floorplan designs[C]//Proceedings of the 23rd IEEE /ACM Design Automation Conference,1986:101-107
  • 3Shen Zion Cien,Chu Chris C N.Bounds on the number of slicing,mosaic,and general floorplans[J].IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems,2003,22(10):1354-1361
  • 4Chang Yun-Chih,Chang Yao-Wen,Wu Guang-Ming,et al.B* -Trees:a new representation for non-slicing floorplans[C] //Proceedings of IEEE/ACM Design Automation Conference,Los Angeles,California,2000:458-463
  • 5Lee Hsun-Cheng,Chang Yao-Wen,Hsu Jer-Ming,et al.Multilevel floorplanning/placement for large-scale modules using B* -trees[C] //Proceedings of IEEE/ACM Design Automation Conference,Anaheim,California,2003:812-817
  • 6Guo Pei-Ning,Cheng Chung-Kuan,Yoshimura Takeshi.An OTree representation of non-slicing floorplan and its application[C]//Proceedings of IEEE/ACM Design Automation Conference,New Orleans,Louisiana,1999:268-273
  • 7LinJ M,Chang Y W.TCG:a transitive closure graph-based representation for nonslicing floorplans[C] //Proceedings of the38th IEEE/ACM Design Automation Conference,Las Vegas,Nevada,2001:764-769
  • 8Murata H,Fujiyoshi K,Nakatake S,et al.VLSI module placement based on rectangle-packing by the sequence-pair[J].IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems,1996,15(12):1518-1524
  • 9Hong X,et al.Corner block list:an effective and efficient topological representation of nonslicing floorplan[C] //Proceedings of IEEE/ACM International Conference on Computer Aided Design,San Jose,California,2000:8-12
  • 10Kim Jae-Gon,Kim Yeong-Dae.A linear programming-based algorithm for floorplanning in VLSI design[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2003,22(5):584-592

共引文献5

同被引文献46

  • 1张旭,冯恩民.卫星舱三维布局优化模型及判断不干涉性算法[J].运筹与管理,2004,13(3):15-19. 被引量:5
  • 2王惠娟,王金敏,李乃华.机械产品布局设计的分层递阶求解模型[J].现代制造工程,2004(2):111-113. 被引量:3
  • 3赵长虹,陈建,周电,周晓方,孙劼.基于权重的超大规模集成电路布图规划算法[J].计算机辅助设计与图形学学报,2006,18(7):994-998. 被引量:6
  • 4王伶俐,杨萌,周学功.深亚微米FPGA结构与CAD设计[M].北京:电子工业出版社,2008.
  • 5刘战,须自明,王国章,于宗光.一种用于FPGA布局的模拟退火算法[J].微计算机信息,2007,23(05Z):184-186. 被引量:1
  • 6Betz V, Rose J. VPR: a new packing, placement and routing tool for FPGA research [C] //Proceedings of the 7thInternational Workshop on Field-Programmable Logic and Applications. London: Springer, 1997: 1-10.
  • 7Tsay R S, Kuh E S, Hsu C P. Proud:a sea-of-gates placement algorithm [C] //Proceedings of the 25th ACM/IEEE Design Automation Conferenee. Los Alamitos:IEEE Computer Society Press, 1988:44-56.
  • 8RoyJ A, Papa D A, Adya S N, et al. Capo: robust and scalable open-source rain-cut floorplacer [C] //Proceedings ofIEEE/ACM International Conference on Physical Design. New York: ACM Press, 2005: 224-226.
  • 9Viswanathan N, Chu C C N. FastPlace: efficient analytical placement using cell shifting, iterative local refinement and ahybrid net model [C]//Proceedings of International Symposium on Physical Design. New York: ACM Press, 2004 :26-33.
  • 10Kleinhands J M, Sigl G, Johannes F M, et al. GORDIAN: VLSI placement by quadratic programming and slicingoptimization [J]. IEEE Transactions on Computer-Aided Design, 1991, 10(3):356-365.

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